On Database-Free Authentication of Microelectronic Components
| Autor: | Swarup Bhunia, Patanjali Slpsk, Fengchao Zhang, Amit Ranjan Trivedi, Shubhra Deb Paul |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
Authentication
Boundary scan Database Computer science Overhead (engineering) Physical unclonable function Vulnerability 02 engineering and technology Integrated circuit design Adversary computer.software_genre 020202 computer hardware & architecture Digital signature Hardware and Architecture 0202 electrical engineering electronic engineering information engineering Message authentication code Electrical and Electronic Engineering Field-programmable gate array computer Digital watermarking Software |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29:149-161 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/tvlsi.2020.3039723 |
| Popis: | Counterfeit integrated circuits (ICs) have become a significant security concern in the semiconductor industry as a result of the increasingly complex and distributed nature of the supply chain. These counterfeit chips may result in performance degradation, profit reduction, and reputation risk for the manufacturer. Therefore, developing effective countermeasures against such malpractices is becoming severely crucial. Physical unclonable function (PUF)-based authentication methods have the potential to mitigate these challenges. However, PUF-based solutions are restrained by several factors, such as additional design efforts and significant area/power overhead, struggle to maintain and update challenge–response pairs (CRPs) database, and the vulnerability to machine learning (ML) attacks. In this article, we address these challenges by developing a novel database-free and enrolment-free hardware authentication approaches, i.e., a digital watermark metric for ICs. To enable efficient database-free hardware integrity verification without enrolment, first, we transform the intrinsic variations in circuit parameters, e.g., boundary scan chain (BSC) path delays in the joint test action group (JTAG) chain into robust digital signatures. Then, we perform statistical analysis on a small pilot unit of authentic chips to create a robust watermark for a complete batch of chips, which jointly captures the characteristics of the physical layout, the manufacturing process, and the foundry. The increasing complexity in the current state-of-the-art designs makes it extremely hard for an adversary to perfectly clone such statistical characterization of circuit parameters using counterfeit or compromised hardware. Besides, the proposed approach requires no additional design or hardware overhead in IC design since it utilizes an embedded structure, which inherently exists within the chips. It also obviates the design house from characterizing each manufactured chip instance, reducing overall testing cost. A path-delay measurement method at a high resolution based on clock phase sweep is introduced to measure the delay values effectively. The proposed intrinsic identifier-based authentication approach is validated by performing emulation on FPGAs and also by conducting physical measurements on custom-made printed circuit boards (PCBs). The reliability of the generated watermarks is evaluated with environmental temperature fluctuations and the aging effect. |
| Databáze: | OpenAIRE |
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