A 553 K-transistor LISP processor chip
| Autor: | C.-H. Shaw, C. Hewes, Douglas J. Matzke, J.F. Sexton, K.N. Ruparel, M.D. Ales, Patrick W. Bosshart, T. Shridhar, Mi-Chang Chang, K. Fasham, A.L. Lee, K.K. Chau, Theodore W. Houston, D. Stark, S.L. Lusky, S.S. Mahant-Shetti, V. Kalyan, C.C. Hoac |
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| Rok vydání: | 1987 |
| Předmět: |
Very-large-scale integration
business.industry Cycles per instruction Computer science Hardware_PERFORMANCEANDRELIABILITY Integrated circuit Chip law.invention Read-write memory Microprocessor CMOS law Embedded system Hardware_INTEGRATEDCIRCUITS Lisp Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING Electrical and Electronic Engineering business computer Computer hardware computer.programming_language |
| Zdroj: | IEEE Journal of Solid-State Circuits. 22:808-819 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/jssc.1987.1052817 |
| Popis: | The authors describe a LISP microprocessor which includes over 550 K transistors, has 114 K of on-chip RAM, and runs instructions in a single 30-ns clock cycle. The chip is implemented in 1.25-/spl mu/m double-level-metal (DLM) CMOS, has 224 pins, and is packaged in a custom pin-grid array. The microinstruction and macroinstruction sets of this chip are compatible with an existing LISP processor. An extensive discussion of test features designed into the processor chip is given. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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