| Autor: |
Shoji Yoshida, Takeshi Okagaki, Naoya Watanabe, Kazunori Onozawa, Makoto Yabuuchi, Kenji Yamaguchi, Takumi Hasegawa, Koji Nii, Miho Yokota |
| Rok vydání: |
2015 |
| Předmět: |
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| Zdroj: |
Proceedings of the 2015 International Conference on Microelectronic Test Structures. |
| DOI: |
10.1109/icmts.2015.7106140 |
| Popis: |
Test structures for measuring characteristics of MOS components in 28 nm high-k metal-gate (HKMG) Ternary Content-Addressable memory (TCAM) bitcell are implemented. Proposed TCAM bitcell are including pull-down (PD) and pass-gate (PG) NMOSs, pull-up (PU) PMOSs and search NMOSs, which are built up based on standard 6T SRAM bitcell. It can achieve the small area but symmetrical layout could not be implemented. Each MOS characteristic is measured by test structure and observed over 20 mV V t offset for each PD and PG NMOS pairs due to asymmetrical layout, whereas there is no difference in PU-PMOS pair. From measurement results we estimate the bit error rates on the supply voltage for TCAM array and predict that the TCAM V min for read-operation becomes worse by 42 mV at 5.3-sigma condition compared to that of standard SRAM array. Based on measured bitcell characteristics we designed and fabricated 80-Mbit TCAM test chips with appropriate redundancies, achieving below 740 mV V min at 250 MHz operation at 25°C and 85°C. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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