Parallel graph reduction with the PACE architecture

Autor: F. Z. Ieromnimon, M. E. Waite, T. J. Reynolds
Rok vydání: 2002
Předmět:
Zdroj: PDP
DOI: 10.1109/empdp.1996.500618
Popis: The PACE architecture is an extensible, distributed memory multiprocessor that is designed specifically to support the graph reduction model of computation. PACE differs from most other research projects in this area in that it advocates the use of a specially designed processor, rather than currently available devices, as the basic replicable node. We present the design of a prototype version of the new processor, together with the latest results obtained by simulating the parallel execution of example programs on both a detailed Verilog description of the hardware and a much faster C simulator (arrays of up to 200 processors are simulated).
Databáze: OpenAIRE