Silicon Nitride Thickness Profile Tuning to Reduce Shallow Trench Isolation Variability in Planar CMOS
| Autor: | Jaana S. Rajachidambaram, John Gumpher, Sharma Vineet, Brett Yatzor, Chia Hao Tsao |
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| Rok vydání: | 2016 |
| Předmět: |
0209 industrial biotechnology
Materials science business.industry Oxide 02 engineering and technology Chemical vapor deposition Condensed Matter Physics Temperature measurement Industrial and Manufacturing Engineering Electronic Optical and Magnetic Materials chemistry.chemical_compound 020901 industrial engineering & automation Planar chemistry CMOS Silicon nitride Shallow trench isolation Electronic engineering Deposition (phase transition) Optoelectronics Electrical and Electronic Engineering business |
| Zdroj: | IEEE Transactions on Semiconductor Manufacturing. 29:217-222 |
| ISSN: | 1558-2345 0894-6507 |
| Popis: | A method for low pressure chemical vapor deposition of silicon nitride that utilizes thermal ramping during multiple deposition steps is demonstrated in a 300 mm vertical batch reactor. Temperature ramp rates in each heater zone are optimized to deposit silicon nitride films with edge-thin (or dome-shape) thickness profiles across the length of the reactor. This process is compatible with real-time automated tuning schemes commonly used to control thickness across all reactor zones. No significant film degradation or interface formation is detected in silicon nitride films deposited using the multi-deposition technique. This technique is applied to deposit pad silicon nitride with an edge-thin thickness profile, and is incorporated into a planar CMOS shallow trench isolation integration scheme to improve post-CMP oxide step height uniformity. |
| Databáze: | OpenAIRE |
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