Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application
| Autor: | Bruce Woolery, Abdur Rahman, J.-Y. Yeh, P. Bai, M. Jamil, K. Phoa, C.-H. Jan, Curtis Tsai, G. Curello, J. Hicks, M. S. Rahman, Joodong Park |
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| Rok vydání: | 2013 |
| Předmět: |
Engineering
Negative-bias temperature instability business.industry Transistor Electrical engineering Time-dependent gate oxide breakdown Hardware_PERFORMANCEANDRELIABILITY law.invention Reliability (semiconductor) CMOS law Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering business Metal gate Hardware_LOGICDESIGN High-κ dielectric |
| Zdroj: | 2013 IEEE International Reliability Physics Symposium (IRPS). |
| Popis: | Transistor reliability characterization studies are reported for a state of the art 22nm 3-D tri-gate HK/MG SoC technology with logic and HV I/O transistor architecture. TDDB, BTI and HCI degradation modes for logic and I/O transistors are studied and excellent reliability is demonstrated. In order to simultaneously integrate logic and HV 3-D tri-gate transistors with robust reliability, the importance of process optimization is emphasized. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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