| Autor: |
Yingxuan Li, Mark Horowitz, C. Huang, Kevin S. Donnelly, Kun-Yung Ken Chang, J. Wei, Stefanos Sidiropoulos, Simon Li |
| Rok vydání: |
2003 |
| Předmět: |
|
| Zdroj: |
IEEE Journal of Solid-State Circuits. 38:747-754 |
| ISSN: |
0018-9200 |
| DOI: |
10.1109/jssc.2003.810045 |
| Popis: |
This paper describes the design and implementation of a quad high-speed transceiver cell fabricated in 0.13-/spl mu/m CMOS technology. The clocking circuit of the cell employs a dual-loop architecture with a high-bandwidth core phase-locked loop (PLL) and low-bandwidth digitally controlled interpolators. To achieve low jitter while maintaining low power consumption, the dual-loop PLL uses two on-chip linear regulators of different bandwidths, one for the core and the other for the interpolator loop. The prototype chip operates from 400 Mb/s to 4 Gb/s with a bit error rate of |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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