| Autor: |
Jussi Ryynanen, Mikko Kaltiokallio, Kari Stadius, Marko Kosunen, Olli Viitala |
| Rok vydání: |
2015 |
| Předmět: |
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| Zdroj: |
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). |
| DOI: |
10.1109/rfic.2015.7337773 |
| Popis: |
This paper presents a low power wideband blocker detector consisting of an under-sampling SAR ADC connected to the RF input node of a wideband mixer-first receiver. The original carrier frequency of the blocker is determined from folded spectra by using three FFTs sampled at different rates whose ratios correspond to prime numbers. The detector is targeted for blocker power levels between 0 and −30 dBm within frequency range of 0.7–2.7 GHz. The achieved ADC maximum SNDR of 28 dB, together with 10 dB input buffer gain control, provide sufficient blocker detection sensitivity in the desired range. The measured sampled input signal spectra show the designed circuits capability to simultaneously detect narrowband and wideband blockers. The reconstructed folded spectrum shows the original blocker frequencies. The power consumption of the wideband detector is only 7 mW, while the receiver consumes 42 mW. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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