New Double Fault Tolerant Full Adder Design for Real-Time Applications
| Autor: | T. N. S. R. Revanth, S. V. Raghu Sekhar Reddy, Sarada Musala, Aruna Kumari Neelam |
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| Rok vydání: | 2020 |
| Předmět: |
Very-large-scale integration
021110 strategic defence & security studies Adder Computer science business.industry 0211 other engineering and technologies Fault tolerance Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Fault (power engineering) Chip Logic gate Double fault business Computer hardware Electronic circuit |
| Zdroj: | 2020 International Conference on Communication and Signal Processing (ICCSP). |
| DOI: | 10.1109/iccsp48568.2020.9182130 |
| Popis: | Using VLSI more number of transistors can be embedded on a single chip. As the space between transistors or circuits decreasing the system or chip is more susceptible to faults. Fault tolerant systems required to avoid inaccurate results. Full adder is basic building block for addition of multi bit numbers. The existing structure proposed is unable to detect fault in sum for some combinations. The proposed design can detect concurrent faults in both sum and carry. And also the proposed structure can repair the faults itself. This self repairing full adder structure can detect and repair the single and multiple faults. The proposed structure gives 100% error recovery. The circuit is simulated using Cadence tool and verified the functionality. |
| Databáze: | OpenAIRE |
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