System Verification and Analysis of ALU for RISC Processor
| Autor: | H R Archana, S V Sunil, H T Bhavana, T. Sanjana |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
Reduced instruction set computing
business.industry Computer science CPU cache 020206 networking & telecommunications 02 engineering and technology law.invention Instruction set Microprocessor law Embedded system 0202 electrical engineering electronic engineering information engineering Verilog 020201 artificial intelligence & image processing Execution unit Central processing unit Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING business Harvard architecture computer computer.programming_language |
| Zdroj: | 2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS). |
| DOI: | 10.1109/icaccs51430.2021.9442045 |
| Popis: | Reduced Instruction Set Computing (RISC) processors have wide selection of applications performance on speed and better cache memory. The advanced RISC microprocessors are extensively used for many of the complicated systems. Reduced Instruction set Computing (RISC) is a CPU (Central Processing Unit) design mechanism that displays fundamental instruction set and performs better after comparison with the other microprocessor architecture and has the ability to perform commands per instruction through microprocessor cycles. The proposed processor is designed using Harvard architecture, having separate instruction and data memory. Building of a fully synthesizable 32-bit RISC processor with Fetching unit, Decoding unit, Data and instruction memory, and Execution unit. The RISC Processor design is synthesized and implemented using Xilinx ISE Tool and simulated using I-sim. A 32-bit RISC is simulated and checked through VIO IP cores. We can use debug feature to drive and monitor signals that are present on the real hardware. This work is intended with Verilog HDL and implemented with the help of development board using Artix-7 FPGA device. The outcomes of performance are evaluated in terms of area, timing performance and maximum frequency of operation. The RISC processor compares earlier comparable architecture with efficient developments. |
| Databáze: | OpenAIRE |
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