A pipelined interface for high floating-point performance with precise exceptions
| Autor: | S. Iacobovici |
|---|---|
| Rok vydání: | 1988 |
| Předmět: |
Floating point
Coprocessor Computer science business.industry Pipeline (computing) Floating-point unit Double-precision floating-point format Parallel computing law.invention Arithmetic logic unit Microprocessor Hardware and Architecture law Embedded system Execution unit Central processing unit Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering business Software |
| Zdroj: | IEEE Micro. 8:77-87 |
| ISSN: | 0272-1732 |
| DOI: | 10.1109/40.542 |
| Popis: | Two options are presented that were considered for a pipelined interface between a central processing unit (CPU) and a floating-point coprocessor (FPU), along with the CPU recovery mechanisms that provide precise floating-point exceptions for each option. The first option supports parallel execution of both floating-point and integer instructions, while the second option pipelines only the execution of floating-point instructions. The use of the second option in National Semiconductor's 32532/32580 processor cluster because it offers high performance with significantly lower complexity. The 32532 microprocessor features a pipelined slave protocol that hides the CPU-FPU communication overhead for most floating-point instructions by pipelining their execution. A simple recovery mechanism implemented within the CPU maintains the precision of floating-point exceptions. As a result, the 32532 microprocessor supports very high floating point performance without sacrificing software compatibility with previous Series 32000 CPU-FPU clusters. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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