Low Power FGSRAM Cell Using Sleepy and LECTOR Technique
| Autor: | Kanan Bala Ray, Shivalal Patro, Sushanta K. Mandal |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Engineering
Control and Optimization Power gating Computer Networks and Communications business.industry Transistor Sram cell Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Leakage power 020202 computer hardware & architecture law.invention Power supply voltage CMOS Hardware and Architecture law Signal Processing Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering business Cadence Information Systems Leakage (electronics) |
| Zdroj: | Indonesian Journal of Electrical Engineering and Computer Science. 4:333 |
| ISSN: | 2502-4760 2502-4752 |
| DOI: | 10.11591/ijeecs.v4.i2.pp333-340 |
| Popis: | In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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