DESIGN OF RISC PROCESSOR USING VHDL
| Autor: | S. D. Mali, Sarika Kadam |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Reduced instruction set computing
Computer science business.industry 020208 electrical & electronic engineering 020206 networking & telecommunications 02 engineering and technology Embedded system VHDL 0202 electrical engineering electronic engineering information engineering Hardware_ARITHMETICANDLOGICSTRUCTURES business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION computer computer.programming_language |
| Zdroj: | International Journal of Research -GRANTHAALAYAH. 4:131-138 |
| ISSN: | 2350-0530 2394-3629 |
| DOI: | 10.29121/granthaalayah.v4.i6.2016.2646 |
| Popis: | The aim of the paper is to design a 16-bit RISC processor. It is having five stage pipelining which is designed using VHDL. RISC processors have a unique feature called pipelining. Pipelining is used to make processor faster. In Pipelining instruction cycle is divided into parts so that more than one instruction can be operated in parallel. Number of instructions are designed for this processors. Multiplier is also designed using ADD instruction. Proposed instructions are simulated using Xilinx ISE 13.1i. The processor is synthesized using Spartan-3A XC3S50A XILINX Tool. |
| Databáze: | OpenAIRE |
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