A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs
| Autor: | Mrunal Patel, Shenghsun Cho, Michael Ferdman, Han Chen, Peter Milder |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Functional verification business.industry Computer science media_common.quotation_subject 02 engineering and technology Application software computer.software_genre 01 natural sciences 020202 computer hardware & architecture Software Debugging Virtual machine Server Embedded system 0103 physical sciences 0202 electrical engineering electronic engineering information engineering business Field-programmable gate array computer PCI Express media_common |
| Zdroj: | FPGA |
| Popis: | The need for high-performance and low-power acceleration technologies in servers is driving the adoption of PCIe-connected FPGAs in datacenter environments. However, the co-development of the application software, driver, and hardware HDL for server FPGA platforms remains one of the fundamental challenges standing in the way of wide-scale adoption. The FPGA accelerator development process is plagued by a lack of comprehensive full-system simulation tools, unacceptably slow debug iteration times, and limited visibility into the software and hardware at the time of failure. In this work, we develop a framework that pairs a virtual machine and an HDL simulator to enable full-system co-simulation of a server system with a PCIe-connected FPGA. Our framework enables rapid development and debugging of unmodified application software, operating system, device drivers, and hardware design. Once debugged, neither the software nor the hardware requires any changes before being deployed in a production environment. In our case studies, we find that the co-simulation framework greatly improves debug iteration time while providing invaluable visibility into both the software and hardware components. |
| Databáze: | OpenAIRE |
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