SAR ADCs in parallel [time-interleaved] converter arrays

Autor:	Ron Kapusta
Rok vydání:	2015
Předmět:	Engineering Interleaving Time interleaved business.industry Hardware_INTEGRATEDCIRCUITS Electronic engineering ComputerSystemsOrganization_SPECIAL-PURPOSEANDAPPLICATION-BASEDSYSTEMS business Cmos process Power (physics) Jitter
Zdroj:	CICC
DOI:	10.1109/cicc.2015.7338441
Popis:	• Time-interleaved SAR ADCs are a major focus of active development • Power and area efficiency of SAR architecture suits itself very well to interleaving • Architecture scale well with advancing CMOS process — Process-limited FOM S (jitter) improves with device speed • Many techniques have been needed to enable high-performance, high-speed interleaved systems.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::9e2ef236ac187483ef4ab119617eba76 https://doi.org/10.1109/cicc.2015.7338441 Zobrazit plný text záznamu