| Autor: |
Adam R. Waite, James Schaffranek, Jon Scholl, Matt Sutter, Adam G. Kimura, Glen D. Via |
| Rok vydání: |
2020 |
| Předmět: |
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| Zdroj: |
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE). |
| DOI: |
10.1109/paine49178.2020.9337733 |
| Popis: |
This paper reviews the decomposition of a fabricated Serial Peripheral Interface (SPI) that was manufactured in a 130 nm process node technology to establish a verification and validation methodology for baselining microelectronics assurance. The fabricated SPI goes through a delayering process where each target layer is captured and imaged using a Raith 150 Chipscanner. The features for each layer are extracted allowing a GDSII layout file to be generated and subsequent design netlist to be recovered. The extracted GDSII was compared to the original reference GDSII, exposing additional fill cells that were added to the design at the foundry. The recovered netlist was validated as logically equivalent to the original golden design netlist and was simulated in the original verification testbench, passing 100% of the original model checks. By passing the GDSII comparison, functional model checks, and logical equivalence checks, the fabricated SPI was determined to be trusted. A methodology for establishing an assurance baseline root-of-trust has been proven. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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