A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance

Autor:	Shih-Wei Wang, Ke-Horng Chen, Shen-Yu Peng, Yao-Yi Yang, Yu-Huei Lee, Alex Chun-Hsien Wu, Chen-Chih Huang, Chao-Cheng Lee, Ching-Yuan Yeh, Ming-Hsin Huang, Chao-Chang Chiu, Ying-Hsi Lin
Rok vydání:	2012
Předmět:	Engineering Switched-mode power supply business.industry Pipeline (computing) Amplifier Hardware_PERFORMANCEANDRELIABILITY Chip Phase-locked loop CMOS Asynchronous communication Hardware_INTEGRATEDCIRCUITS Electronic engineering Hybrid power business
Zdroj:	VLSIC
DOI:	10.1109/vlsic.2012.6243848
Popis:	A 50nA quiescent current asynchronous digital-LDO (DLDO) integrated with the PLL-modulated switching regulator (SWR) exhibits the hybrid power management operation. The proposed bidirectional asynchronous wave pipeline (BAWP) in the asynchronous DLDO realizes the Fast-DVS (F-DVS) operation within tens of nano-seconds. The SWR with the leading phase amplifier achieves on-the-fly DVS and 94% peak efficiency, as well as improves 5.6 times MIPS performance through hybrid operation. The fabricated chip occupies 1.04mm2 in 40nm CMOS.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::9da00facbc2797b02baa800d195d6068 https://doi.org/10.1109/vlsic.2012.6243848 Zobrazit plný text záznamu