65nm Low Power (LP) SOI Technology on High Resistivity (HR) Substrate for WLAN and Mmwave SOCs

Autor:	Frederic Gianesello, Nicolas Planes, Baudouin Martineau, Sebastien Haendler, Christine Raynaud, Patricia Touret, Georges Guegan
Rok vydání:	2009
Předmět:	High resistivity Materials science business.industry Electrical engineering Silicon on insulator Optoelectronics Substrate (printing) business Power (physics)
Zdroj:	ECS Transactions. 19:257-264
ISSN:	1938-6737 1938-5862
DOI:	10.1149/1.3117416
Popis:	We present a 65nm RF SOI CMOS technology, targeted as Low Power (LP) to serve mobile applications. The integration has been made on High Resistive (HR) back substrate 300mm SOI wafers from SOITEC to improve performances in high frequency range, compared to bulk [1, 2]. For the first time, low leakage SRAM (Isb< 10pA at 0.9V, 25{degree sign}C, for 0.62µm2 and 0.52µm2 cells) are integrated on these HR wafers, and the paper reports a 30% power reduction in operation for a given maximum speed, compared to similar SRAM design on bulk. Furthermore, we have demonstrated a 21% measured power-delay product reduction compared to bulk, at 125{degree sign}C, on loaded ring oscillators.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::9d93b7050b0677567c0a47104501395b https://doi.org/10.1149/1.3117416 Zobrazit plný text záznamu