| Autor: |
Zaid El-Mekki, F. Schleicher, Frederic Lazzarino, D. Trivkovic, Zsolt Tokei, B. De-Wachter, S. V. Gompel, L. Halipre, E. Vancoille, S. Decoster, G. Muroch, Thomas Witters, L. Dupas, O. Varela-Pereira, B. Briggs, Quoc Toan Le, Harinarayanan Puliyalil, Christopher J. Wilson, Philippe Leray, N. Jourdan, I. Demonie, C. Lorant, Joost Bekaert, Nancy Heylen, Y. Kimura, Rogier Baert, M. H. van der Veen, J. Versluijs, Miroslav Cupak, Patrick Verdonck, K. Croes, Manoj Jaysankar, Anne-Laure Charley, J. Heijlen, J. Uk-Lee, Ivan Ciofi, Y. Drissi, V. Vega-Gonzalez, S. Paolillo, H. Vats, D. Montero, L. Rynders, Els Kesters, M. Ercken, A. Lesniewska, R. Kim, Lieve Teugels, T. Webers |
| Rok vydání: |
2020 |
| Předmět: |
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| Zdroj: |
2020 IEEE International Electron Devices Meeting (IEDM). |
| Popis: |
The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated. Place-and-route (PnR) simulations of the Power Delivery Network (PDN) proved IR-drop reduction with respect to the stacked-via configuration. SV first and SV last integration approaches were electrically tested using full barrierless ruthenium (Ru) on a dielectric low-k 3.0. A maximum AR = 3.8 was achieved with ~2.4 times lower resistance than the alternative stacked-via configuration. Thermal shock tests produced no SV failure after 1000 cycles between -50 °C and 125 °C, and 250 hours. Time-dependent-dielectric-breakdown (TDDB) tests between SV and M2 lines gave a TTF 63.2% (at 1 MV/cm) > 10 years, when 3 M2 tracks are blocked. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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