| Autor: |
Shozo Saito, Y. Okada, K. Natori, Shuso Fujii, S. Sawada, O. Ozawa, M. Sato, S. Shinozaki |
| Rok vydání: |
2005 |
| Předmět: |
|
| Zdroj: |
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. |
| DOI: |
10.1109/isscc.1986.1156942 |
| Popis: |
A single mask set DRAM architecture with a 1MW×1b or 256KW×4b organization, selectable by bonding configurations, will be discussed. With a CMOS half V cc cc generator, a standby current of 50μA has been achieved. A triple layer polysilicon N-well measuring 3.24μm2has resulted in a chip size of 4.4×12.3mm2with an access time of 56ns. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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