Floating–Point Fused Multiply–Add under HUB Format
| Autor: | Julio Villalba-Moreno, Sonia Gonzalez-Navarro, Javier Hormigo |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Floating point
Multiply–accumulate operation Application-specific integrated circuit Square root Computer science 0202 electrical engineering electronic engineering information engineering Key (cryptography) 02 engineering and technology Arithmetic Complex number 020202 computer hardware & architecture Power (physics) |
| Zdroj: | ARITH |
| DOI: | 10.1109/arith48897.2020.00010 |
| Popis: | The Half-Unit-Biased (HUB) format has interesting advantages for implementing floating-point arithmetic which has been proved for the four basic arithmetic operations as well as square root. Nevertheless, although Floating-point Fused Multiply-add (FMA) operation (AxB + C) is one of the most important and complex arithmetic instructions in modern processors, FMA operation for HUB numbers has not been confronted yet. In this paper, we present a design to deal with this operation under HUB format. The key points to turn the conventional FMA architecture into a HUB unit are explained. Comparing the ASIC implementation of a HUB FMA unit with the conventional one, the former reduces the required area and power up to 38% and 35%, respectively, for single-precision. For BFloat16, the HUB FMA increases the speed a 15%, and even then, reduces the area and power by 26% and 12%, respectively. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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