| Popis: |
This paper describes a design methodology of novel macro-cells for next generation ASIC libraries that has a low-power consumption and high-speed operation. In order to satisfy the desired characteristics, novel architectures of adder, multiplier, and shifter are proposed. Further, automatic layout generation programs are proposed. They are designed on the basis of the standard-cell approach and they generate the layouts of the proposed macro-cells from 8-bit to 64-bit. The proposed macro-cells are designed with a novel compound logic that consists of both CMOS logic and pass-transistor logic. They are fabricated with 0.25 /spl mu/m 1-poly 5-metal CMOS process, and have desired experimental results. |
