Channel-Stress Enhancement Characteristics for Scaled pMOSFETs by Using Damascene Gate With Top-Cut Compressive Stress Liner and eSiGe

Autor:	Satoru Mayuzumi, Y. Tateshita, T. Ohno, Masanori Tsukamoto, Daisuke Kosemura, Hitoshi Wakabayashi, Shinya Yamakawa, Munehisa Takei, Naoki Nagashima, Atsushi Ogura
Rok vydání:	2009
Předmět:	Electron mobility Materials science business.industry Analytical chemistry Copper interconnect Electronic Optical and Magnetic Materials Stress (mechanics) Logic gate MOSFET Optoelectronics Electrical and Electronic Engineering business Metal gate AND gate High-κ dielectric
Zdroj:	IEEE Transactions on Electron Devices. 56:2778-2784
ISSN:	1557-9646 0018-9383
Popis:	A damascene-gate process enhances the drivability in the shorter gate length region, as compared to a conventional gate-first process for pFETs with compressive stress SiN liners and embedded source/drain SiGe. The origin of the gate length effect for damascene-gate pFETs is studied by using UV-Raman spectroscopy and stress simulation. Moreover, the relationship between channel strain and channel width is analyzed, and the enhancement effect of the drivability on channel width is demonstrated. It is found that channel strain is considerably enhanced with the narrower channel width and shorter gate length by the process combination of the damascene gate and stress enhancement techniques. Owing to the enhancement effects of both channel width and gate length, a high drive current of 1090 muA/mum at Vds = Vgs = -1.0 V and Ioff = 100 nA/mum is achieved for the damascene-gate pFET with 0.3-mum channel width and 40-nm gate length.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::9bd8869190d774759dca478ee951fffb https://doi.org/10.1109/ted.2009.2031002 Zobrazit plný text záznamu