A 224 PW 260 PPM/°C Gate-Leakage-Based Timer for Ultra-Low Power Sensor Nodes with Second-Order Temperature Dependency Cancellation
| Autor: | Satoru Miyoshi, David Blaauw, Dennis Sylvester, Makoto Yasuda, Jongyup Lim, Mehdi Saligane, Taekwang Jang, Masaru Kawaminami |
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| Rok vydání: | 2018 |
| Předmět: |
Ultra low power
Materials science business.industry 020208 electrical & electronic engineering Electrical engineering 02 engineering and technology Temperature measurement Power budget Voltage variation Logic gate 0202 electrical engineering electronic engineering information engineering Wireless Timer business Leakage (electronics) |
| Zdroj: | VLSI Circuits |
| DOI: | 10.1109/vlsic.2018.8502374 |
| Popis: | A key challenge in the design of on-chip wake-up timers for compact wireless sensor nodes is to achieve high timing accuracy over temperature and supply voltage variation within an ultra-low power budget. We propose a gate-leakage-based frequency-locked timer with first- and second-order cancellation achieving 260 ppm/°C from −5 to 95°C. The timer consumes 224 pW at 90 Hz output frequency with 0.93%/V supply voltage dependence in the 1.1-3.3 V range. |
| Databáze: | OpenAIRE |
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