Sequential Equivalence Checking for Clock-Gated Circuits

Autor:	Hamid Savoj, Robert K. Brayton, Alan Mishchenko
Rok vydání:	2014
Předmět:	Digital electronics Sequential logic business.industry Formal equivalence checking Clock gating Computer Graphics and Computer-Aided Design Logic synthesis Electrical and Electronic Engineering business Retiming Algorithm Software Mathematics Logic optimization Asynchronous circuit
Zdroj:	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33:305-317
ISSN:	1937-4151 0278-0070
Popis:	Sequential logic synthesis often leads to substantially easier equivalence checking problems, compared to general-case sequential equivalence checking (SEC). This paper theoretically investigates when SEC can be reduced to a combinational equivalence checking (CEC) problem. It shows how the theory can be applied when sequential transforms are used, such as sequential clock gating, retiming, and redundancy removal. The legitimacy of such transforms is typically justified intuitively, by the designer or software developer believing that the two circuits reach the same state after a finite number of cycles, and no difference is observed at the outputs due to fanin non-controllability and fanout non-observability effects.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::9b12794658312fb5fb87459112f38b83 https://doi.org/10.1109/tcad.2013.2284190 Zobrazit plný text záznamu