A 16 DIP, 64 kbit, static MOS-RAM
| Autor: | S. Matsue, M. Sakamoto, H. Yamanaka, Toshio Wada, H. Yamamoto |
|---|---|
| Rok vydání: | 1981 |
| Předmět: |
Dynamic random-access memory
Hardware_MEMORYSTRUCTURES Materials science business.industry Chip size Electrical engineering Dissipation Multiplexing Cell size law.invention Software_SOFTWAREENGINEERING law Optoelectronics Static random-access memory Electrical and Electronic Engineering business Access time |
| Zdroj: | IEEE Journal of Solid-State Circuits. 16:488-491 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | A 64K/spl times/1 bit fully static MOS-RAM has been fabricated. For the purpose of replacement of 64 kbit dynamic RAM, this static RAM has been designed to be assembled in a standard 300 mil 16 pin DIP. It is the first time address multiplexing has been in static RAMs. The device with multiple addressing and improved row decoder employs a double poly Si layer and a 1.5 /spl mu/m design rule which is achieved by advanced process technology. As a result, the RAM has a 11.0 /spl mu/m/spl times/26.5 /spl mu/m (291.5 /spl mu/m/SUP 2/) cell size and a 3.84 mm/spl times/7.40 mm (28.40 mm/SUP 2/) chip size. The address access time is less than 150 ns with an active power dissipation of 400 mW. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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