A quasi-power-gated low-leakage stable SRAM cell
| Autor: | Pradeep S. Nair, Savithra Eratne, Eugene John |
|---|---|
| Rok vydání: | 2010 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Power gating Materials science business.industry Transistor Electrical engineering Hardware_PERFORMANCEANDRELIABILITY law.invention Hardware_GENERAL law Low-power electronics MOSFET Hardware_INTEGRATEDCIRCUITS Inverter Static random-access memory business NMOS logic Hardware_LOGICDESIGN Leakage (electronics) |
| Zdroj: | 2010 53rd IEEE International Midwest Symposium on Circuits and Systems. |
| DOI: | 10.1109/mwscas.2010.5548705 |
| Popis: | Leakage power dissipation and stability continues to be a major concern in deep-submicron SRAM cell design. In this paper, a quasi-power-gating approach that reduces the leakage power dissipation in an SRAM cell while maintaining stability is proposed. As compared to a standard 6-transistor SRAM, it consists of four additional NMOS transistors. In the active mode, the cell is activated by enabling two NMOS transistors in the pull-down path of the inverter. In the idle mode, a quasi-power-gating scheme is employed to reduce leakage by utilizing stack effect. It was found that this cell resulted in about 39.54 percent and 30.5 percent leakage power savings at a supply voltage value of 1V and 300mV respectively. A stability increase was also observed when compared to the standard non-power-gated 6-transistor SRAM cell. |
| Databáze: | OpenAIRE |
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