| Autor: |
K. Nakos, K. Babionitakis, George Lentaris, J. Sifnaios, Gregory Doumenis, George Georgakarakos, N. Vlassopoulos, Dionysios Reisis |
| Rok vydání: |
2006 |
| Předmět: |
|
| Zdroj: |
ICECS |
| DOI: |
10.1109/icecs.2006.379846 |
| Popis: |
Video technology evolution has boosted the need for the H.264/AVC encoder with real-time performance. In order to meet such need the present paper presents a VLSI H.264/AVC encoder architecture and the relevant details on design and implementation of the specific modules. The encoder design complies with the reference software encoder of the standard and follows the baseline profile level 3.0. The encoder constitutes an IP-core and/or stand-alone solution targeting to low area applications. The architecture achieves maximum throughput of 30 frames/sec with frame size 1024times768. Results and performance measurements of the entire encoder have been validated on FPGA and VLSI .18 mum. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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