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Bottleneck analysis has been used to understand the underlying performance of the different components that make up a CPU. The goal is to improve overall performance through the effective use of different architectural components. Through the use of benchmarks, users can gain a better understanding of performance issues, by tracking how bottlenecks are being handled by the architecture. A comparison of bottlenecks generated by different settings sheds information into the performance capabilities of the platform being tested. The issue is that standard techniques might not have complete information on how bottlenecks evolve between settings relative to a reference configuration. We complement the Top-Down microarchitectural analysis method with a normalization technique from the field of economics, purchasing power parity (PPP). This pairing makes it possible to better understand the relative difference between bottlenecks when normalizing with a reference thread configuration. In this study, we find a number of Top-Down identified bottlenecks that had large relative differences that standard, non-normalized, Top-Down metrics failed to identify. |
