A digital MDLL using switched biasing technique to reduce low-frequency phase noise
| Autor: | Shen-Iuan Liu, Chang-Cheng Huang, Ting-Kuei Kuan, Chi-Huan Chiang |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Engineering
business.industry 020208 electrical & electronic engineering Biasing 02 engineering and technology Low frequency 020202 computer hardware & architecture Power (physics) CMOS Logic gate Phase noise Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering business Jitter Voltage |
| Zdroj: | A-SSCC |
| DOI: | 10.1109/asscc.2016.7844145 |
| Popis: | A digital multiplying delay-locked loop (DMDLL) is presented to reduce the low-frequency phase noise and lower the power. The main divider is also turned off to reduce the power. The digitally-controlled oscillator uses the switched biasing technique to reduce the low-frequency phase noise. This DMDLL is fabricated in 40-nm CMOS technology and its active area is 0.0088 mm2. The output frequency of the DMDLL ranges from 100 to 1050MHz for a supply voltage of 1.1V. The integrated RMS jitter is 2.68ps and the power consumption is 1.51mW at the output frequency of 1050MHz. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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