A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS
| Autor: | Sandipan Kundu, Rajeev K. Dokania, Kai Yu, Ajay Balankutty, Frank O'Mahony, Skyler Weaver, Amr Elshazly, Jihwan Kim, Hyung Seok Kim |
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| Rok vydání: | 2018 |
| Předmět: |
Computer science
business.industry 020208 electrical & electronic engineering Bandwidth (signal processing) Transmitter Electrical engineering Bandwidth extension 02 engineering and technology 01 natural sciences Backward compatibility 010309 optics CMOS Modulation 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Transceiver Symbol rate business Higher-order modulation Jitter |
| Zdroj: | ISSCC |
| DOI: | 10.1109/isscc.2018.8310204 |
| Popis: | The rapidly growing demand for high-bandwidth data communication infrastructure has fueled the industry to develop ultra-high-speed/density wireline links compliant with electrical interface standards such as CEI-56G and 802.3bs–400GbE. Recent publications have demonstrated CMOS transmitters (TX) operating from 50–64Gb/s [1-4], and early planning for the next generation of 100Gb/s+ wireline standards is underway. Long-reach wireline standards at 56Gb/s have largely adopted a PAM-4 modulation scheme that maintains the same symbol rate as the previous generation of 28Gb/s NRZ transceivers. For 112Gb/s transceivers, however, higher order modulation (e.g., PAM-8/16) is unlikely to be adopted due to the tradeoff in SNR and backward compatibility. Therefore, the symbol rate for 112Gb/s PAM-4 must be doubled relative to the previous generation, which requires circuit bandwidth and jitter performance to improve by roughly a factor of two. In addition, the energy efficiency of the link must be maximized to keep local power delivery and system power consumption within practical limits. This paper presents a reconfigurable 56GS/s 3-tap FFE TX that operates up to 112Gb/s with PAM-4 or at 56Gb/s with NRZ modulation. The TX employs a quarter-rate architecture, a 1-UI pulse-generator-based 4:1 serializer combined with a CML driver, a multi-segment π-coil for pad bandwidth extension, and per-lane duty-cycle detection/correction (DCD/DCC) and quadrature-error detection/correction (QED/QEC) circuits. The TX is implemented in a 10nm FinFET CMOS technology and benefits from improvements to transistor drive strength, interconnect electro-migration/resistance, and overall area scaling [5]. |
| Databáze: | OpenAIRE |
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