Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime
| Autor: | Ching-Yuan Chen, Kai-Hsun Chen, Jiun-Lang Huang |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
Computer science
020208 electrical & electronic engineering Probabilistic logic Process (computing) Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Logic level Automatic test pattern generation 020202 computer hardware & architecture Reliability engineering Logic gate Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Central processing unit Testability Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | DDECS |
| DOI: | 10.1109/ddecs.2019.8724660 |
| Popis: | Reconvergence has been recognized as the main reason for ATPG backtrack. It induces not only more, but also prolonged backtracks and causes more severe performance degradation than expected. In this paper, we propose a reconvergence-aware testability measure to better guide the ATPG justification process. Experiment results show that the proposed method significantly decreases the ATPG runtime, especially for circuits with deep logic level, by up to 76%. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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