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Deformations of metal interconnects, cracks in interlayer dielectrics and passivation layers in combination with plastic packaging are still a major reliability concern for integrated circuit power semiconductors. In order to describe and understand the failure mechanism and its root cause, already a lot of work has been done in the past. However for the first time it is demonstrated that stress induced in the inter layer dielectric (ILD) can be the main cause of failure for a power switching device. The impact of metallization scheme on the amount of electrical failures of a power switching device was investigated in detail. It was found that with replacing a single layer metallization by a double layer metallization, the number of electrical failures reduced drastically. This improvement was achieved by two mechanisms. First, the stress induced by the molding compound (MC) through the metallization on the ILD under the metallization reduced significantly. Secondly the stress in the passivation located at the foot of the bottom metallization was relocated to the foot of the top passivation. At that location it is far less likely the passivation cracks would propagate into the ILD. These observations were confirmed by 3-D FEM simulations. The simulations enabled to locate and quantify the critical stress levels leading to electrical failures. As a result, the improved metallization scheme could lead to a distinct reduction of the principal stress at the most critical positions and, consequently, to an improvement of the reliability of the devices. |
