STRAIGHT: Hazardless Processor Architecture Without Register Renaming
| Autor: | Takahiro Notsu, Seiya Akaki, Ryota Shioya, Teruo Ishihara, Shuichi Sakai, Yutaro Bessho, Katsuhiro Yoda, Akifumi Fukuda, Toru Koizumi, Hidetsugu Irie, Satoshi Nakae |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Out-of-order execution Computer science Instruction window Register renaming 02 engineering and technology Parallel computing Operand computer.software_genre 01 natural sciences 020202 computer hardware & architecture Microarchitecture law.invention Instruction set Microprocessor law Superscalar 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Compiler Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING Instruction-level parallelism Machine code computer |
| Zdroj: | MICRO |
| DOI: | 10.1109/micro.2018.00019 |
| Popis: | The single-thread performance of a processor improves the capability of the entire system by reducing the critical path latency of programs. Typically, conventional superscalar processors improve this performance by introducing out-of-order (OoO) execution with register renaming. However, it is also known to increase the complexity and affect the power efficiency. This paper realizes a novel computer architecture called "STRAIGHT" to resolve this dilemma. The key feature is a unique instruction format in which the source operand is given based on the distance from the producer instruction. By leveraging this format, register renaming is completely removed from the pipeline. This paper presents the practical Instruction Set Architecture (ISA) design, the novel efficient OoO microarchitecture, and the compilation algorithm for the STRAIGHT machine code. Because the ISA has sequential execution semantics, as in general CPUs, and is provided with a compiler, programming for the architecture is as easy as that of conventional CPUs. A compiler, an assembler, a linker, and a cycle-accurate simulator are developed to measure the performance. Moreover, an RTL description of STRAIGHT is developed to estimate the power reduction. The evaluation using standard benchmarks shows that the performance of STRAIGHT is 18.8% better than the conventional superscalar processor of the same issue-width and instruction window size. This improvement is achieved by STRAIGHT's rapid miss-recovery. Compilation technology for resolving the possible overhead of the ISA is also revealed. The RTL power analysis shows that the architecture reduces the power consumption by removing the power for renaming. The revealed performance and efficiencies support that STRAIGHT is a novel viable alternative for designing general purpose OoO processors. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|