Fault Tolerant Technique for Processor Control Path to Mitigate SEUs in FPGA

Autor: B S Chandrasekhar, S Deepanjali, Noor Mahammad Sk
Rok vydání: 2022
Zdroj: 2022 IEEE International Symposium on Smart Electronic Systems (iSES).
DOI: 10.1109/ises54909.2022.00018
Databáze: OpenAIRE