Power-Efficient VLSI Realization of a Complex FSM for H.264/AVC Bitstream Parsing

Autor:	Ke Xu, Kong-Pang Pun, Cheong-Fat Chan, Chiu-Sing Choy
Rok vydání:	2007
Předmět:	Very-large-scale integration Finite-state machine Computer science business.industry Clock gating Data_CODINGANDINFORMATIONTHEORY Reduction (complexity) Gate count CMOS Embedded system Electrical and Electronic Engineering business Bitstream Computer hardware Decoding methods Hardware_LOGICDESIGN
Zdroj:	IEEE Transactions on Circuits and Systems II: Express Briefs. 54:984-988
ISSN:	1558-3791 1549-7747
DOI:	10.1109/tcsii.2007.903785
Popis:	This paper presents a systematic, power-efficient design methodology for the complex finite state machine (FSM) implementation of H.264/AVC decoding. The proposed FSM orchestrates the decoding steps and predicts the type of incoming codeword based on current FSM states and input symbols. The VLSI realization shows a gate count reduction of 14% and an average power reduction of 37.6% in real-time video decoding. The FSM has been implemented with UMC 130 nm 1P6M CMOS technology, and it consumes 38.3 muW at 1.08 V when running at 20 MHz.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::990122cf1fe80ae7cacf44f3b8662cbf https://doi.org/10.1109/tcsii.2007.903785 Zobrazit plný text záznamu