Post porosity plasma protection integration at 48 nm pitch
| Autor: | Terry A. Spooner, Joe Lee, Alfred Grill, Huai Huang, Eric G. Liniger, B. Peethala, Willi Volksen, Hosadurga Shobha, Krystelle Lionti, Chao-Kun Hu, Griselda Bonilla, Theodorus E. Standaert, Donald F. Canaperi, Elbert E. Huang, Geraud Dubois, Teddie Magbitang, James Hsueh-Chung Chen, Daniel C. Edelstein |
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| Rok vydání: | 2016 |
| Předmět: |
Materials science
business.industry Copper interconnect 02 engineering and technology Plasma Dielectric 010402 general chemistry 021001 nanoscience & nanotechnology 01 natural sciences Capacitance 0104 chemical sciences Plasma-enhanced chemical vapor deposition Node (physics) Multiple patterning Electronic engineering Optoelectronics 0210 nano-technology Porosity business |
| Zdroj: | 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC). |
| DOI: | 10.1109/iitc-amc.2016.7507715 |
| Popis: | Integration of high porosity low-k dielectrics faces major challenges as the porosity weakens the dielectric, resulting in severe plasma induced damage (PID) and difficulties in profile control. Post porosity plasma protection (P4) integration strategy addresses those challenges by strengthening the dielectric via porosity refill during the integration steps. Realization of P4 integration at an advanced node is nontrivial. In this paper, we demonstrate the feasibility of the P4 integration scheme in a dual damascene double patterning 48 nm pitch test vehicle with a plasma enhanced chemical vapor deposited (PECVD) k = 2.4 inter-layer dielectric (ILD). In addition, initial results of applying P4 with a PECVD k = 2.2 ILD show promise in reducing capacitance at 48 nm pitch and beyond. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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