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We theoretically and experimentally investigate how the field-effect mobility (MFE) depends on the gate capacitances (CI) in solution-processed oxide semiconductor (OS) thin-film transistors (TFTs). With recently developed solution-based techniques, high quality OS films can be deposited onto flexible substrates at low temperatures, which accelerate applying of flexible, transparent, and ink-jet printable OS TFTs to future mobile display and electronics. Meanwhile, another important issue is to sustainably use of portable devices using integrated OS TFT circuits for a long time. Empirically, Increasing CI has been used to increase the drain current (ID) for high-performance and low-energy consuming OS TFTs, which is based on a theory of conventional metal-oxide-semiconductor field-effect transistors (MOSFETs): ID∝CI. However, it has been observed that incremental features of ID as increasing CI in solution-processed OS TFTs are quite different to that of MOSFETs. It is because disordered metal ions and dense grain boundaries in the solution-processed OSs make MFE depend on total number of accumulated electrons. Thus, MFE relies on CI, and ID cannot be linear relationship to CI. Therefore, grasping the relationship between MFE and CI in theoretical manner is important to realize high-performance, low-operational voltage devices, and it is also useful to design, optimize, and integrate OS TFT circuits. The disordering nature of solution-processed OSs can be classified into nanocrystalline and amorphous states, which are determined by how many numbers of metal ions component are contained. When the number of metal ion component is ‘1’, such as ZnO, InO2, and SnO2, the solution-processed OS films have nanocrystalline phase. As the number of metal ion component is larger than ‘1’(for example, ZnSnO, InGaZnO, InZnO), the states of the OS films are amorphous. Although electronic properties of both amorphous and nanocrystalline OS films arising from their atomic arrangements are different to each other, the CI-dependent-MFE characteristics have been observed by two following features experimentally. First, with high-CI conditions, the maximum-MFE values of the OS TFTs can be achieved with low gate voltages (VG) than that with low-CI conditions. Second, the maximum-MFE values with gate insulator comprising of high-k dielectric materials is higher than that comprising of low-k dielectric materials, within the associated VG regimes. However, how the MFE values is determined by the CI values and how gate-insulator properties (ex, dielectric constant) affects the maximum-MFE values have not been intensively investigated yet. Here, we systematically performed an investigation of the CI-dependent MFE features. We developed theoretical models representative of the solution-processed OS TFTs, where multiple-trapping-and-release (MTR) and hopping percolation mechanisms are used for explaining the electrical conductivity of nanocrystalline and amorphous OS films, respectively. For both theoretical models, we derived a single-piece expression that shows how the MFE value and the operational voltage can be determined by the CI value. We successfully verified the developed analytic formula by using fabricated solution-processed ZnO and ZnSnO TFTs. At low-VG regions (~4 V), the ZnO TFTs shows that its MFE varies from 0.066 to 6.01 cm2 / V sec following MFE ∝~ CI1.66, while the ZnSnO TFTs shows MFE∝~CI0.41. Furthermore, we investigated how the dielectric constant of gate insulators affects the maximum MFE values. |
