Investigations of performance enhancement in a poly-Si nanowire FET featuring independent double-gated configuration and its nonvolatile memory applications
| Autor: | Yu-Chia Chang, Tiao-Yuan Huang, Horng-Chih Lin, Wei-Chen Chen, Hsing-Hui Hsu |
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| Rok vydání: | 2010 |
| Předmět: |
Fabrication
Materials science Silicon business.industry Nanowire chemistry.chemical_element Nanotechnology Hardware_PERFORMANCEANDRELIABILITY Non-volatile memory chemistry Nanoelectronics Logic gate Hardware_INTEGRATEDCIRCUITS Optoelectronics Field-effect transistor business Quantum tunnelling Hardware_LOGICDESIGN |
| Zdroj: | Proceedings of 2010 International Symposium on VLSI Technology, System and Application. |
| DOI: | 10.1109/vtsa.2010.5488911 |
| Popis: | Charge-trapping SONOS devices featuring nanowire (NW) and independent double-gated (IDG) structure are fabricated and characterized. The mechanism leading to DG output current performance enhancement is investigated. Taking advantage of the separated-gated property, the back-gate bias effect is used to probe its impacts on programming efficiency. It is also discovered that reduced NW thickness leads to stronger back-gate effects. |
| Databáze: | OpenAIRE |
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