SOI 90-nm ring oscillator sub-ps model-hardware correlation and parasiticaware optimization leading to 1.94-ps switching delay

Autor:	Paul A. Hyde, Richard Q. Williams, Jonghae Kim, W. Clark, V. Karam, B.J. Gross, Jean-Olivier Plouchart, Robert Trzcinski, Kun Wu, Myung-Hee Na, J. Mc Cullen
Rok vydání:	2006
Předmět:	Computer science business.industry Monte Carlo method Silicon on insulator Statistical model Hardware_PERFORMANCEANDRELIABILITY Ring oscillator Integrated circuit layout Reference circuit Hardware_INTEGRATEDCIRCUITS Electronic engineering Inverter business Computer hardware Voltage
Zdroj:	IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
DOI:	10.1109/iedm.2005.1609540
Popis:	This paper reports the SOI 90 nm statistical model to hardware correlation achieved over a broad voltage, temperature and a variety of five different ring oscillators. Monte Carlo simulations were performed and compared with the measured circuit statistical population. A sub-ps model to hardware correlation accuracy was achieved between the mean hardware and simulated delays. Based on the model validation, a parasitic aware layout optimization was performed on a constrained and an unconstrained inverter leading to a 5 and 66 % reduction in delay of the inverter reference circuit. The unconstrained parasitic aware optimization achieves a record inverter switching delay of 1.94 ps
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::984165a78ca46309da00bcf41234fdf8 https://doi.org/10.1109/iedm.2005.1609540 Zobrazit plný text záznamu