A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology
| Autor: | Katsuaki Sakurai, Feng Lu, Kenro Kubota, Hiroshi Sugawara, Yoshihiko Shindo, Steve Choi, Junji Musha, Yusuke Ochi, Hao Nguyen, Hiroshi Nakamura, Yee Koh, Yasuhiro Suematsu, Ryo Fukuda, Tomoko Nishiuchi, Spiros Georgakis, Keyur Payak, Masatsugu Kojima, Sanad Bushnaq, Naoki Kobayashi, Kwang-ho Kim, Hiroe Minagawa, Manabu Sato, Yuuki Shimizu, Naoaki Kanagawa, Susumu Fujimura, Teruo Takagiwa, Kenichi Abe, Takahiro Shimizu, Toshiki Hisada, Taichi Wakui, Hiroshi Maejima, Susumu Ozawa, Makoto Miakashi, Srinivas Rajendra, Kazushige Kanda, Hiroshi Yoshihara, Namas Raghunathan, Akihiro Imamoto, Koji Hosono, Dong He, Satoshi Inoue, Masatsugu Ogawa, Seungpil Lee, Jumpei Sato, Fumihiro Kono, Yuui Shimizu, Kazuhiko Satou, Takuya Futatsuyama, Venky Ramachandra, Naohito Morozumi, Weihan Wang, Tomoharu Hashiguchi, Hicham Haibi, Noboru Shibata, Takatoshi Minamoto, Xu Li, Kouichirou Yamaguchi, Toshifumi Hashimoto, Takahiro Yamashita, Ken Cheah, Mitsuhiro Abe, Tetsuya Kaneko, Tadashi Yasufuku, Takahiro Sugimoto |
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| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Hardware_MEMORYSTRUCTURES Sense amplifier business.industry Computer science 020208 electrical & electronic engineering String (computer science) 02 engineering and technology 01 natural sciences Die (integrated circuit) Flash memory Flash (photography) 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Key (cryptography) business Word (computer architecture) Computer hardware |
| Zdroj: | ISSCC |
| DOI: | 10.1109/isscc.2018.8310321 |
| Popis: | The first multi-layer stacked 3D Flash memory was proposed as BiCS FLASH in 2007 [1]. Since then, memory bit density has grown rapidly due to the increase in the number of stacked layers from continuous 3D technology innovations. On the other hand, the multi-level-cell technology, which was initially proposed for 2D Flash, has also been adopted to 3D Flash memories. The first 3b/cell 32-layer Flash was presented in 2015 [2], followed by a 48-layer one in 2016 [3], and a 64-layer one in 2017 [4,5]. This paper describes a 512Gb 3b/cell 3D Flash memory in a 96-word-line-layer BiCS FLASH technology. This work implements three key technologies to improve performance: (1) a string based start bias control scheme achieves a 7% shorter program time; (2) a smart V t -tracking read improves read retry performance by minimizing the tracking time and supporting a program suspend read function, and; (3) a low-pre-charge sense-amplifier bus scheme reduces both the power consumption and the data-transfer time between the sense amplifier (SA) and the data cache by half. Figure 20.1.1 shows the die micrograph and the summary of the key features of the chip. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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