Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing
| Autor: | Sumit Khalapure, R K Siddharth, Y B Nithin Kumar, M H Vasantha |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Spurious-free dynamic range
Differential nonlinearity business.industry Dynamic range Computer science 020208 electrical & electronic engineering 020206 networking & telecommunications 02 engineering and technology Flash ADC Effective number of bits Least significant bit Integral nonlinearity Logic gate Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Hardware_ARITHMETICANDLOGICSTRUCTURES business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Computer hardware |
| Zdroj: | ISVLSI |
| DOI: | 10.1109/isvlsi.2017.108 |
| Popis: | This paper proposes the different way of designing standard-cell based flash ADC in order to increase its input dynamic range. It includes implementation of 5-bit flash ADC for fully automated digital synthesis. The input dynamic range is increased by including 5-input logic gates. The proposed architecture results in Differential Non-Linearity (DNL) of ±0.206 LSB and Integral Non-Linearity (INL) of ± 0.218 LSB range. This standard-cell based flash ADC has Effective Number of Bits (ENOB) of 4.78 bits at the sampling frequency of 400 MS/s. The Spurious-Free Dynamic Range (SFDR) of 42.05 dB is achieved at an input frequency of 1.95 MHz. |
| Databáze: | OpenAIRE |
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