A Low-Power 0.5–6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs

Autor:	Xuewen Jiang, Kenny Hsieh, Jason Gong, Didem Turker, Siok Wei Lim, Jose Anup P, Jay Im, Arianne Roldan, Fu-Tai An, Vassili Kireev, Ken Chang, Parag Upadhyaya, Daniel Wu, Jafar Savoj
Rok vydání:	2013
Předmět:	Engineering business.industry Wireline Transmitter Power integrity Hardware_PERFORMANCEANDRELIABILITY Phase-locked loop CMOS Low-power electronics Hardware_INTEGRATEDCIRCUITS Electronic engineering Insertion loss Electrical and Electronic Engineering Transceiver business
Zdroj:	IEEE Journal of Solid-State Circuits. 48:2582-2594
ISSN:	1558-173X 0018-9200
Popis:	This paper describes the design of a 0.5-6.6 Gb/s fully-adaptive low-power quad transceiver embedded in low-leakage 28 nm CMOS FPGAs. Integration techniques enable the utilization of the transceiver in FPGAs with both wire-bond and flip-chip packages and resolve significant challenges with receiver input and transmitter output insertion loss, power integrity, ESD, and reliability. The transceiver clocking network provides continuous operation range up to the maximum speed and incorporates two wide-range ring-based PLLs for enhanced clocking flexibility. The receiver front-end utilizes a 3-stage CTLE with wide input common-mode to remove the post-cursor ISI. The CTLE is fully adaptive using an LMS algorithm and edge-based equalization. The transmitter utilizes a 3-tap FIR. The transceiver achieves BER 10-15 at 6.6 Gb/s over a 20 dB loss channel. Power consumption is 129 mW from 1.2 V and 1 V supplies.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::96cad245e500b90f0621bff748044dfb https://doi.org/10.1109/jssc.2013.2274824 Zobrazit plný text záznamu