A novel heterogeneous FPGA architecture based on memristor-transistor hybrid approach
| Autor: | M. Khurram Bhatti, Umer Farooq, M. Hassan Aslam |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Engineering
business.industry Time to market 020208 electrical & electronic engineering Transistor 020206 networking & telecommunications 02 engineering and technology Memristor Reconfigurable computing Programmable logic array law.invention Computer architecture Application-specific integrated circuit law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Routing (electronic design automation) Field-programmable gate array business Hardware_LOGICDESIGN |
| Zdroj: | DTIS |
| DOI: | 10.1109/dtis.2016.7483890 |
| Popis: | Heterogeneous Field Programmable Gate Arrays (FPGAs) are now considered a practical alternative to Application Specific Integrated Circuits (ASICs) thanks to their generalized reconfigurable nature and fast time to market. However, the area, performance gap between FPGAs and ASICs is still quite huge. In this work, we propose a novel memristor-transistor hybrid heterogeneous FPGA architecture that gives better area results as compared to conventional transistor-only heterogeneous FPGA. Memristor-transistor based hybrid building blocks of heterogeneous FPGA are designed and simulated in this work. Results show that hybrid blocks are 25%–60% smaller compared to transistor-only blocks. Furthermore, a generalized exploration flow is also proposed where open source and indigenously developed tools give end-to-end exploration experience. Ten heterogeneous benchmarks are placed and routed on proposed and conventional heterogeneous FPGAs using the exploration flow. Results show that proposed hybrid architecture, on average, consumes 56% less logic area, 60% less routing area; thus leading to 59% total area gain compared to conventional architecture. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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