FPGA Based Efficient Feed forward FFT Architecture
| Autor: | V Monica, C K Narayanappa, S L Gangadharaiah |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
Computer science
020208 electrical & electronic engineering Fast Fourier transform Feed forward 02 engineering and technology Parallel computing Sample (graphics) 020202 computer hardware & architecture Search engine 0202 electrical engineering electronic engineering information engineering Multiplier (economics) Booth's multiplication algorithm Hardware_ARITHMETICANDLOGICSTRUCTURES Architecture Field-programmable gate array |
| Zdroj: | 2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). |
| DOI: | 10.1109/rteict42901.2018.9012113 |
| Popis: | Feed forward FFT architectures provide an efficient method to compute FFT with a better hardware utilization, by making use of parallelism and pipelining concepts. Multipliers form an integral part of FFT architectures. Right choice of multiplier leads to improved area and speed. In this paper, we present a study on rotator allocation based Radix-2 feed forward FFT architectures with two different multipliers introduced into the architecture individually. The two architectures are designed considering 16 sample points with 4 inputs arriving at a time in parallel. The comparison of the architectures shows that the architecture with multiplier based on Modified Booth algorithm is more area efficient and has an improvement in speed. The synthesis is done on Virtex-6 FPGA, XC6VSX475T-l FF1156. |
| Databáze: | OpenAIRE |
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