| Autor: |
Maryse Cournoyer, Hiroyuki Mori, Ravi K. Bonam, Marc A. Bergendahl, Paul S. Andry, Dishit P. Parekh, Isabel de Sousa, Kamal K. Sikka, Aakrati Jain, Pascale Gagnon, Rama Divakaruni, Thomas A. Wassick, Ed Cropp, Hongqing Zhang, Yang Liu, Sayuri Kohara, Catherine Dufort |
| Rok vydání: |
2021 |
| Předmět: |
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| Zdroj: |
2021 IEEE 71st Electronic Components and Technology Conference (ECTC). |
| Popis: |
We introduce a new packaging technology termed as Direct Bonded Heterogeneous Integration (DBHi) where a Si-bridge is directly bonded to and in between processor chips using Cu pillars, allowing high-bandwidth low-latency low-power communication between the chips. The DBHi package structure, test vehicle design, and bond and assembly details are first described. The test vehicle package consists of chips with standard interconnect pitch where they join to a laminate chip-carrier and fine-pitch pads in the region where the chips joins to a bridge. The bridge has Cu pillars correspondingly mating to the pads on the chips. The bond and assembly sequence starts with first joining the silicon chips and bridge using a thermocompression bonding process followed by a mass reflow join of the chips to the laminate. The assembly is then underfilled and capped using specialized techniques. Mechanical modeling was extensively used to simulate the DBHi structure and assembly process to allow material selection and reliability prediction. The mechanical models were calibrated using warpage measurements. The stress/strain reliability metrics of the DBHi package are compared to a non-bridge package of the same dimensions. Results show that the main focus should be directed towards ensuring a robust assembly process as the standard reliability stress/strain metrics of the DBHi package are very similar to a non-bridge package. Thermal measurements using chip heaters and temperature sensors were conducted to calibrate a numerical thermal model of the DBHi package. The thermal model was exercised to show the relation between the allowable chip and bridge power densities for the particular package size and cooling conditions. DBHi test packages were created using the best-known assembly process and then measured for continuity performance. A variety of inter- and intra-bridge daisy chain nets were incorporated into the test vehicle for continuity measurements. Post-assembly continuity measurements demonstrated a robust assembly process for multiple rounds of assembly. Reliability performance was demonstrated using standard JEDEC tests of thermal cycling, aging, and temperature/humidity. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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