| Popis: |
A full capacitance model for amorphous oxide semiconductors Thin Film Transistors (AOSTFTs) is validated in dynamic regime using a Ring Oscillator of 19 stages fabricated and measured, describing the model in Verilog-A language. In this paper, we obtained good results and coincidence between the dynamic characteristics of the circuit measured and modeled. The modeled characteristics where obtained using the SmartSpice tool from Silvaco. The model includes the effect of the different overlaps capacitance present in the structures of the a-IGZO TFTs analyzed, which is an important factor used to determine the oscillator performance of the devices. We also analyze the dynamic behavior of the circuit when the internal capacitances of the TFTs increase or decrease, with respect to the real value, obtaining the expected behavior. In this work we also show how was considered the effect of the time in the internal capacitances of the transistors, using the Spice simulator. The model was validated for different supply voltages, for 10, 15 and 20 V, in all cases, the agreement between characteristics simulated and measured was good. |
