On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform
| Autor: | Chih-Chi Cheng, Chung-Jr Lian, Chao-Tsung Huang, Liang-Gee Chen, Ching-Yeh Chen |
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| Rok vydání: | 2007 |
| Předmět: |
Very-large-scale integration
Discrete wavelet transform Signal processing Finite impulse response business.industry Computer science Signal compression Memory bandwidth Image processing computer.file_format Embedded system MPEG-4 JPEG 2000 Line (geometry) Media Technology Electrical and Electronic Engineering business computer Algorithm Data compression Image compression |
| Zdroj: | IEEE Transactions on Circuits and Systems for Video Technology. 17:814-822 |
| ISSN: | 1051-8215 |
| DOI: | 10.1109/tcsvt.2007.897106 |
| Popis: | The on-chip line buffer dominates the total area and power of line-based 2-D discrete wavelet transform (DWT). In this paper, a memory-efficient VLSI implementation scheme for line-based 2-D DWT is proposed, which consists of two parts, the wordlength analysis methodology and the multiple-lifting scheme. The required wordlength of on-chip memory is determined firstly by use of the proposed wordlength analysis methodology, and a memory-efficient VLSI implementation scheme for line-based 2-D DWT, named multiple-lifting scheme, is then proposed. The proposed wordlength analysis methodology can guarantee to avoid overflow of coefficients, and the average difference between predicted and experimental quality level is only 0.1 dB in terms of PSNR. The proposed multiple-lifting scheme can reduce not only at least 50% on-chip memory bandwidth but also about 50% area of line buffer in 2-D DWT module. |
| Databáze: | OpenAIRE |
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