A Cross-Layer Approach for Early-Stage Power Grid Design and Optimization
| Autor: | Cheng Zhuo, Houle Gan, Wei-Kai Shih, Alaeddin Aydiner |
|---|---|
| Rok vydání: | 2015 |
| Předmět: |
Flexibility (engineering)
Scheme (programming language) Engineering Power gating business.industry Power integrity Topology (electrical circuits) computer.file_format Power optimization Power (physics) Hardware and Architecture Electronic engineering Common Power Format Electrical and Electronic Engineering business computer Software computer.programming_language |
| Zdroj: | ACM Journal on Emerging Technologies in Computing Systems. 12:1-20 |
| ISSN: | 1550-4840 1550-4832 |
| Popis: | Power integrity has become increasingly important for sub-32nm designs. Many prior works have discussed power grid design and optimization in the post-layout stage, when design change is inevitably expensive and difficult. In contrast, during the early stage of a development cycle, designers have more flexibility to improve the design quality. However, there are several fundamental challenges at early stage when the design database is not complete, including extraction, modeling, and optimization. This article tackles these fundamental issues of early-stage power grid design from architecture to layout. The proposed methods have been silicon validated on 32nm on-market chips and successfully applied to a 22nm design for its early-stage power grid design. The findings from such practices reveal that, for sub-32nm chips, an intrinsic on-die capacitance and power gate scheme may have more significant impact than expected on power integrity, and needs to be well addressed at early stage. |
| Databáze: | OpenAIRE |
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