| Autor: |
J.S. Humble, Patrick Joseph Zabinski, Barry K. Gilbert, E.S. Daniel |
| Rok vydání: |
2006 |
| Předmět: |
|
| Zdroj: |
ISSCC |
| DOI: |
10.1109/isscc.2006.1696273 |
| Popis: |
A clock duty-cycle correction circuit that accepts input duty cycles ranging from 30% to 70% and maintains a user-selectable output duty cycle over a frequency range of 500MHz to 6GHz is demonstrated. The output duty cycle is selectable from 41.25% to 58.75% in 1.25% increments. The circuitry is integrated into a clock-distribution chip which provides 10 identical outputs |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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